Modern data processing systems may perform Boolean operations on a set of signals using dynamic logic circuits. Dynamic logic circuits are clocked. During the precharge phase of the clock, the circuit is preconditioned, typically by precharging an internal node (dynamic node) of the circuit by coupling to a power supply rail. During an evaluate phase of the clock, the Boolean function being implemented by the logic circuit is evaluated in response to the set of input signal values appearing on the inputs during the evaluate phase. (For the purposes herein, it suffices to assume that the input signals have settled to their “steady-state” values for the current clock cycle, recognizing that the input value may change from clock cycle to clock cycle.) Such dynamic logic may have advantages in both speed and the area consumed on the chip over static logic. However, the switching of the output node with the toggling of the phase of the clock, each cycle may consume power even when the logical value of the output is otherwise unchanged.
This may be appreciated by referring to FIG. 1.1 illustrating an exemplary three-input OR dynamic logic gate, and the accompanying timing diagram, FIG. 1.2. Dynamic logic 100 includes three inputs a, b and c coupled to a corresponding gate of NFETs 102a–102c. During an evaluate phase N1 (116) of clock 104, NFET 106 is active, and if any of inputs a, b or c are active, dynamic node 108 is pulled low, and the output OUT goes “high” via inverter 110. Thus, referring to FIG. 1.2, which is illustrative, at t1, input a goes high during a precharge phase N2 of clock 104. During the precharge phase N2 of clock 104, dynamic node 108 is precharged via PFET 112. Half-latch PFET 114 maintains the charge on dynamic node 108 through the evaluate phase, unless one or more of inputs a, b or c is asserted. In the illustrative timing diagrams in FIG. 1.2, input a is “high” having a time interval t1 through t2 that spans approximately 2½ cycles of clock 104, which includes evaluation phases, 116 and 118. Consequently, dynamic node 108 undergoes two discharge-precharge cycles, 124 and 126. The output node similarly undergoes two discharge-precharge cycles, albeit with opposite phase, 124 and 126. Because the output is discharged during the precharge phase of dynamic node 108, even though the Boolean value of the logical function is “true” (that is, “high” in the embodiment of OR gate 100) the dynamic logic dissipates power even when the input signal states are unchanged.
Additionally, dynamic logic may be implemented in a dual rail embodiment in which all of the logic is duplicated, one gate for each sense of the data. That is, each logic element includes a gate to produce the output signal, and an additional gate to produce its complement. Such implementations may exacerbate the power dissipation in dynamic logic elements, as well as obviate the area advantages of dynamic logic embodiments.
Limited switching dynamic logic (LSDL) circuits produce circuits which mitigate the dynamic switching factor of dynamic logic gates with the addition of static logic devices which serve to isolate the dynamic node from the output node. Co-pending U.S. patent application entitled, “CIRCUITS AND SYSTEMS FOR LIMITED SWITCH DYNAMIC LOGIC,” Ser. No. 10/116,612 filed Apr. 4, 2002 and commonly owned, recites such circuits. Additionally, LSDL circuits and systems maintain the area advantage of dynamic logic over static circuits, and further provide both logic senses, that is, the output value and its complement.
A logic buffer is a logic circuit that isolates or “buffers” a logic signal. It may be used to increase the fan-out of a logic signal. In some cases, a buffer also inverts the logic signal, thus a logic inverter may be thought of as an inverting buffer. As with standard logic functions, there may be static and clocked buffers. The LSDL logic technology uses both static devices and LSDL logic devices. In standard LSDL, a buffer is realized by replacing the logic tree with a single device. In this way, a logic signal coupled to the data input is clocked into the LSDL buffer and a latched output and its inversion are generated. Because there are a large number of buffers used in any modern integrated circuit (IC) design, buffers are key and perhaps the primary power contributors in any logic design. This is equally true for LSDL designs.
There is, therefore, a need for an LSDL buffer design that maintains all of the LSDL circuit advantages over other dynamic logic while reducing the dynamic power dissipated.